

cpu registers

 

#define REG_0 0
#define REG_1 1
#define REG_2 2
#define REG_3 3
#define REG_4 4
#define REG_5 5
#define REG_6 6
#define REG_7 7
#define REG_8 8
#define REG_9 9
#define REG_10 10
#define REG_11 11
#define REG_12 12
#define REG_13 13
#define REG_14 14
#define REG_15 15
#define REG_16 16
#define REG_17 17
#define REG_18 18
#define REG_19 19
#define REG_20 20
#define REG_21 21
#define REG_22 22
#define REG_23 23
#define REG_24 24
#define REG_25 25
#define REG_26 26
#define REG_27 27
#define REG_28 28
#define REG_29 29
#define REG_30 30
#define REG_31 31
#define REG_hi 100
#define REG_lo 101
#define REG_hi1 102
#define REG_lo1 103
#define REG_sa 104
#define REG_index 200
#define REG_random 201
#define REG_entrylo0 202
#define REG_entrylo1 203
#define REG_context 204
#define REG_pagemask 205
#define REG_wired 206
#define REG_badvaddr 208
#define REG_count 209
#define REG_entryhi 210
#define REG_compare 211
#define REG_status 212
#define REG_cause 213
#define REG_epc 214
#define REG_prid 215
#define REG_config 216
#define REG_badpaddr 223
#define REG_debug 224
#define REG_perf 225
#define REG_taglo 228
#define REG_taghi 229
#define REG_errorepc 230

#define REG_ccr 300
#define REG_ctr0 301
#define REG_ctr1 302

#define REG_bpc 400
#define REG_iab 402
#define REG_iabm 403
#define REG_dab 404
#define REG_dabm 405
#define REG_dvb 406
#define REG_dvbm 407
#define REG_fpr0 500
#define REG_fpr1 501
#define REG_fpr2 502
#define REG_fpr3 503
#define REG_fpr4 504
#define REG_fpr5 505
#define REG_fpr6 506
#define REG_fpr7 507
#define REG_fpr8 508
#define REG_fpr9 509
#define REG_fpr10 510
#define REG_fpr11 511
#define REG_fpr12 512
#define REG_fpr13 513
#define REG_fpr14 514
#define REG_fpr15 515
#define REG_fpr16 516
#define REG_fpr17 517
#define REG_fpr18 518
#define REG_fpr19 519
#define REG_fpr20 520
#define REG_fpr21 521
#define REG_fpr22 522
#define REG_fpr23 523
#define REG_fpr24 524
#define REG_fpr25 525
#define REG_fpr26 526
#define REG_fpr27 527
#define REG_fpr28 528
#define REG_fpr29 529
#define REG_fpr30 530
#define REG_fpr31 531
#define REG_fcr0 600
#define REG_fcr31 601

/*
* IOP Registers
*/
#define IOP_0 200
#define IOP_1 201
#define IOP_2 202
#define IOP_3 203
#define IOP_4 204
#define IOP_5 205
#define IOP_6 206
#define IOP_7 207
#define IOP_8 208
#define IOP_9 209
#define IOP_10 210
#define IOP_11 211
#define IOP_12 212
#define IOP_13 213
#define IOP_14 214
#define IOP_15 215
#define IOP_16 216
#define IOP_17 217
#define IOP_18 218
#define IOP_19 219
#define IOP_20 220
#define IOP_21 221
#define IOP_22 222
#define IOP_23 223
#define IOP_24 224
#define IOP_25 225
#define IOP_26 226
#define IOP_27 227
#define IOP_28 228
#define IOP_29 229
#define IOP_30 230
#define IOP_31 231

#define IOP_hi 100
#define IOP_lo 101

#define IOP_bpc 303
#define IOP_bda 305
#define IOP_tar 307
#define IOP_bada 308
#define IOP_bdam 309
#define IOP_bpcm 311
#define IOP_status 312
#define IOP_cause 313
#define IOP_epc 314
#define IOP_prid 315

/*
* VU0 Registers
*/
#define VU0VF00 700
#define VU0VF01 701
#define VU0VF02 702
#define VU0VF03 703
#define VU0VF04 704
#define VU0VF05 705
#define VU0VF06 706
#define VU0VF07 707
#define VU0VF08 708
#define VU0VF09 709
#define VU0VF10 710
#define VU0VF11 711
#define VU0VF12 712
#define VU0VF13 713
#define VU0VF14 714
#define VU0VF15 715
#define VU0VF16 716
#define VU0VF17 717
#define VU0VF18 718
#define VU0VF19 719
#define VU0VF20 720
#define VU0VF21 721
#define VU0VF22 722
#define VU0VF23 723
#define VU0VF24 724
#define VU0VF25 725
#define VU0VF26 726
#define VU0VF27 727
#define VU0VF28 728
#define VU0VF29 729
#define VU0VF30 730
#define VU0VF31 731

#define VU0VI00 800
#define VU0VI01 801
#define VU0VI02 802
#define VU0VI03 803
#define VU0VI04 804
#define VU0VI05 805
#define VU0VI06 806
#define VU0VI07 807
#define VU0VI08 808
#define VU0VI09 809
#define VU0VI10 810
#define VU0VI11 811
#define VU0VI12 812
#define VU0VI13 813
#define VU0VI14 814
#define VU0VI15 815
#define VU0VI16 816 // status flag
#define VU0VI17 817 // MAC flag
#define VU0VI18 818 // clipping flag
#define VU0VI19 819 // reserved
#define VU0VI20 820 // R
#define VU0VI21 821 // I
#define VU0VI22 822 // Q
#define VU0VI23 823 // reserved
#define VU0VI24 824 // reserved
#define VU0VI25 825 // reserved
#define VU0VI26 826 // TPC
#define VU0VI27 827 // CMSAR0
#define VU0VI28 828 // FBRST
#define VU0VI29 829 // VPU-STAT
#define VU0VI30 830 // reserved
#define VU0VI31 831 // CMSAR1

/*
* VU1 Registers
*/
#define VU1VF00 900
#define VU1VF01 901
#define VU1VF02 902
#define VU1VF03 903
#define VU1VF04 904
#define VU1VF05 905
#define VU1VF06 906
#define VU1VF07 907
#define VU1VF08 908
#define VU1VF09 909
#define VU1VF10 910
#define VU1VF11 911
#define VU1VF12 912
#define VU1VF13 913
#define VU1VF14 914
#define VU1VF15 915
#define VU1VF16 916
#define VU1VF17 917
#define VU1VF18 918
#define VU1VF19 919
#define VU1VF20 920
#define VU1VF21 921
#define VU1VF22 922
#define VU1VF23 923
#define VU1VF24 924
#define VU1VF25 925
#define VU1VF26 926
#define VU1VF27 927
#define VU1VF28 928
#define VU1VF29 929
#define VU1VF30 930
#define VU1VF31 931

#define VU1VI00 1000
#define VU1VI01 1001
#define VU1VI02 1002
#define VU1VI03 1003
#define VU1VI04 1004
#define VU1VI05 1005
#define VU1VI06 1006
#define VU1VI07 1007
#define VU1VI08 1008
#define VU1VI09 1009
#define VU1VI10 1010
#define VU1VI11 1011
#define VU1VI12 1012
#define VU1VI13 1013
#define VU1VI14 1014
#define VU1VI15 1015
#define VU1VI16 1016 // status flag
#define VU1VI17 1017 // MAC flag
#define VU1VI18 1018 // clipping flag
#define VU1VI19 1019 // reserved
#define VU1VI20 1020 // R
#define VU1VI21 1021 // I
#define VU1VI22 1022 // Q
#define VU1VI23 1023 // reserved
#define VU1VI24 1024 // reserved
#define VU1VI25 1025 // reserved
#define VU1VI26 1026 // TPC
#define VU1VI27 1027 // CMSAR0
#define VU1VI28 1028 // FBRST
#define VU1VI29 1029 // VPU-STAT
#define VU1VI30 1030 // reserved
#define VU1VI31 1031 // CMSAR1

